Article ID: 000082008 Content Type: Troubleshooting Last Reviewed: 07/25/2023

Are there any differences in behavior between RTL simulation and hardware when implementing Rx CDR PLL dynamic reconfiguration using the direct write method of Stratix® V devices?

Environment

  • Quartus® II Subscription Edition
  • PLL Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, you may see differences in behavior between RTL simulation and hardware when implementing Rx CDR PLL dynamic reconfiguration using the direct write method in Stratix® V devices.

    Resolution

    For RTL simulation, you may write the difference in the MIF file using the direct write method. For hardware, the entire Rx CDR PLL MIF file must be written.

    Related Products

    This article applies to 4 products

    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V FPGAs
    Stratix® V GS FPGA