Article ID: 000086200 Content Type: Error Messages Last Reviewed: 09/11/2012

Error: Assignment error: width of source inclk in Signal Assignment Statement must match width of result

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Although the Quartus® II software version 2.0 correctly limits APEX II device PLL input frequencies to 420 MHz, the software incorrectly places this same restriction on high-speed differential (LVDS, LVPECL and HyperTransport™ technology) input clocks. APEX II devices support LVDS input clocks up to 500 MHz, as stated in the solution, What is the maximum high-speed differential (LVDS, LVPECL, and HyperTransport technology) input clock frequency that APEX II devices support?

    This problem was fixed in the Quartus II software version 2.1.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices