Article ID: 000080545 Content Type: Troubleshooting Last Reviewed: 09/29/2014

Where can I get board simulation models for REFCLK pins using HCSL or other I/O standards?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Altera® IBIS, IBIS-AMI or HSPICE models do not include REFCLK models for HCSL or other I/O standards for all devices supporting high speed (GX/GT/GZ) transceivers. 

Resolution

You can simulate this interface using HSSI HSPICE or IBIS-AMI models for transceiver RX pin. Board simulation models are located at SPICE Models for Altera Devices. 

Related articles

Related Products

This article applies to 14 products

Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® IV GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Stratix® II GX FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Stratix® IV GX FPGA
Arria® II GZ FPGA
Arria® II GX FPGA
Stratix® IV GT FPGA
Arria® GX FPGA

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.