Article ID: 000077547 Content Type: Troubleshooting Last Reviewed: 03/27/2015

Stratix® III Device Handbook: Known Issues

Environment

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Description

Issue 287788: Chapter 7 Stratix III Device I/O Features, Version 1.9

The first sentence of LVDS Input On-Chip Termination (RD) section says "a nominal resistance value of 10 ."  But this should say "a nominal resistance value of 100  .."

 

 

Issue 156385: Clock Networks and PLLs in Stratix III Devices, Version 2.0

There are two bullets for requirements when using automatic clock switchover, the first one is incorrect. It says:

"Both clock inputs must be running."

The purpose of automatic clock switchover is to switch between clocks if one stops running. The actual requirement is both clocks need to be running when the FPGA is configured. The bullet should say:

"Both clock inputs must be running when the FPGA is configured."

Issue 10003633, Volume 1, Chapter 4  “TriMatrix Embedded Memory Blocks in Stratix III Devices”,
Version  1.5

Page 4-6 incorrectly states that MLABs can support mixed data widths through emulation via the Quartus®  II software.   Also on page 4-10, it incorrectly states that the Quartus II software can implement mixed width memories in MLABs by using more than one MLAB.

 

Resolution

Resolved Issues

Issue 10002079 , Volume 1 Chapter 13 "IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Devices", Version 1.3.

Information regarding 3.3V VCCPD was added in version 1.4.

Issue 10002636, Volume 1 Chapter 11 "Configuring Stratix III Devices", Version 1.4

Information regarding nCE master and slave connection was fixed in 1.5.

 

Issue 10006577, Vol. 1, Ch. 4: TriMatrix Embedded Memory Blocks in Stratix III Devices, Version 1.7

The Stratix III handbook describes the M9K and M144K memory cells as not being initialized upon power up, and therefore in an unknown state, unless a mif file is specified. 

The correct initialization behavior:

M9K memory cells are initialized to all 0\'s through a default mif file in the Quartus II software.  The user may specify their own initialization of the memory cells through a defined mif file.

The M144K memory cells are not initialized, and therefore come up in an undefined state.  This is to prevent the programming file from being too large. The user may specify their own initialization of the memory cells through a defined mif file.

Issue 10006414, Vol. 1, Ch. 11: Configuring Stratix III Devices, Version 1.9

The tCF2ST1(nCONFIG high to nSTATUS high) timing does not vary according to the tCFG (nCONFIG pulse width). After the nCONFIG is released high, the nSTATUS is released high within the tCF2ST1 maximum specification provided you do not hold the nSTATUS low externally.  

The note associated with the respective table will be changed to say "This value is applicable if you do not delay configuration by externally holding the nSTATUS low."

Issue 10005778, Volume 1, Chapter 6: "Clock Networks and PLLs in Stratix® III Devices" Version 1.8

Note 2 for Table 6-10 also applies to the EP3SL200H780 device.  This device contains 4 PLLs (B1, L2, R2 and T1).

Issue 10005130, Volume 1 Chapter 13 "IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Devices" Version 1.7

Table 13-5 provides an incorrect Version ID (4-bits) in the 32-bit IDCODE for the EP3SL110 device. The correct 4-bit Version ID for this device is 0001.

Issue 10004486, Volume 1, Chapter 8 "External Memory Interfaces in Stratix III Devices" Version 1.8

 

Table 8-10 on page 8-28 is incorrect in showing the clock sources of the DLL. For the EP3SE80, EP3SE110 and EP3SL150 devices with the F780 package, the DLL2 can only be driven by PLL_B1. The DLL3 can’t be driven by any PLL. The DLL4 can only be driven by PLL_R2. The relationships between the dedicated clock pins and the DLLs of Table 8-10 are correct.

Issue 10003564, Volume 1, Chapter 9 "High-Speed Differential I/O Interfaces and DPA in Stratix III Devices", Version 1.5

Figure 9–18 and the note above it incorrectly describe a restriction where single-ended output pins must be at least one LAB row away from differential I/O pins.  There is in-fact no restriction for single ended output pin placement with respect to differential I/O pins. Figure 9-18 and note 4 above it will be removed in a future revision of this chapter.

Issue 10002548, Volume 1 Chapter 8 "External Memory Interfaces in Stratix III Devices", Version 1.4

Note (2) in table 8-5 that You would lose one DQS/DQ group (in any mode) if you use these pins for configuration or as RUP and RDN pins for OCT calibration. This is not true.

DQS/DQSn pins in some of the x4 groups can also be used as Rup/Rdn pins. You cannot use a x4 group for memory interfaces if its pin members are being used as Rup and Rdn pins for OCT calibration. You may be able to use the x8/x9 group that includes this x4 group, if either of the following applies:

- You are not using DM pins with your differential DQS pins

- You are not using complementary or differential DQS pins

 

This is because a x8/x9 group actually comprises 12 pins, as the groups are formed by stitching two groups of x4 mode with 6 total pins each (see table 8-4). A typical x8 or x16 DDR2 SDRAM device consists of one DQS, one DM, and 8 DQ pins which add up to 10 pins. So if you choose your pin assignment carefully, you can use the 2 extra pins for Rup and Rdn. In a DDR3 SDRAM interface, however, you have to use differential DQS, which means that you only have one extra pin. In this case, pick different pin locations for Rup and Rdn pins, in the bank that contains address and command pins.

 

You cannot use Rup and Rdn pins shared with DQS/DQ group pins when using x9 QDRII /QDRII SRAM devices, as the Rup and Rdn pins are dual purpose with the CQn pins. In this case, pick different pin locations for Rup and Rdn pins to avoid conflict with the memory interface pin placement. You have the choice of placing the Rup and Rdn pins in the data write group or in the same bank as the address and command pins.

 

You can also place Rup and Rdn pins with the OCT block in a bank different than the memory interface bank, ensure that the voltage of the bank you place the Rup and Rdn pin in is the same as the memory interface bank voltage.

 

There is no restriction of using x16/x18 or x32/x36 groups that includes the x4 groups whose pin members are being used as Rup and Rdn pins as there are enough extra pins that can be used as DQS pins.

 

Note: You need to pick your DQS/DQ pins manually for the x8, x16/x18, or x32/x36 group whose members are being used for Rup/Rdn as Quartus II may not be able to place this correctly and may give you a no-fit instead.

Issue 10002455, Volume 1 Chapter 11 "Configuring Stratix III Devices", version 1.4

Table 11-14 incorrectly states DATA[0] pin can be used as user I/O once in user mode with Active Serial (AS) configuration scheme. DATA[0] is not available as a user I/O when using the AS configuration scheme.

All AS configuration pins (Data0, DCLK, nCSO, and ASDO) have weak internal pull-up resistors that are always active.

Issue 10002455, Volume 1 Chapter 11 "Configuring Stratix III Devices", Version 1.4

Table 11-14 incorrectly states DATA[0] pin can be used as user I/O once in user mode with Active Serial (AS) configuration scheme. DATA[0] is not available as a user I/O when using the AS configuration scheme.

All AS configuration pins (Data0, DCLK, nCSO, and ASDO) have weak internal pull-up resistors that are always active.


 

Related Products

This article applies to 1 products

Stratix® III FPGAs