Article ID: 000085061 Content Type: Troubleshooting Last Reviewed: 06/29/2014

Why are X's displayed on the reconfig_to_xcvr and reconfig_from_xcvr busses between my Reconfiguration Controller and transceiver PHYs in simulation of Stratix V, Arria V, and Cyclone V transceiver devices?

Environment

  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    X's displayed on some of the bits in the reconfig_to_xcvr and reconfig_from_xcvr busses between the Reconfiguration Controller and transceiver PHYs in simulation of Stratix® V, Arria® V, and Cyclone® V transceiver devices is expected. These bits are reserved for future use, and can be safely ignored.

    If all of either the reconfig_to_xcvr or reconfig_from_xcvr lines display X's this is not normal and connectivity should be checked between the Reconfiguration Controller and the transceiver PHY, as well as clocks and resets to ensure correct operation.

    Related Products

    This article applies to 10 products

    Cyclone® V GX FPGA
    Cyclone® V SX SoC FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Cyclone® V GT FPGA
    Arria® V SX SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V FPGAs

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