Article ID: 000084714 Content Type: Troubleshooting Last Reviewed: 06/28/2016

Does the reset input of the UniPHY-based external memory controllers need to be synchronous to the EMIF clock domains?

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Description No, the global_reset_n and soft_reset_n input signals are synchronized to the various internal clock domains of the UniPHY-based external memory controllers before being used.

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Intel® Programmable Devices