Article ID: 000079307 Content Type: Product Information & Documentation Last Reviewed: 04/19/2016

How can I implement HPS LOAN IO and confirm timing?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Final timing models for LOAN IO are included in the Quartus®  II software version 14.0, and can be used to confirm timing.  Preliminary timing models for LOAN IO are available through a patch for Quartus II software version 13.1 (see related solution below)

    Resolution

    Procedure to use LOAN IO :-

    1. In HPS Megawizard, select “Peripheral Pins” tab
    2. In “Peripherals Mux Table”, select the desired LOAN IO pins
    3. At Qsys "System Contents", export h2f_loan_io conduit
    4. Table 1 shows the generated conduit signal interface in Qsys
    5. Compile the design and generate the preloader with bsp-editor

    Table 1

    Conduit name

    Direction

    Declarations

    ._hps_io_gpio_inst_LOANIOXX   

    Bi-direction

    Declare as top level pin, pin assignment is hardcoded

    ._h2f_loan_io_in [N:0]

    Out

    Output signal pin from FPGA region user logic, input to HPS region

    ._h2f_loan_io_out [N:0]

    In

    Input signal pin from FPGA region user logic, output to HPS region

    ._h2f_loan_io_oe [N:0]

    In

    Output enable for IO buffer at HPS region

    Notes:

    • XX denotes the specific selected HPS IO pin number
    • N denotes the maximum number of HPS IO pins, Cyclone V consists of a maximum of 67 pins while Arria V consists of a maximum of 71 pins
    • No warning messages are shown in Quartus II if user assigns user logic to the wrong loan_io signal pins

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    This article applies to 1 products

    Intel® Programmable Devices