Article ID: 000075281 Content Type: Troubleshooting Last Reviewed: 06/29/2014

Can I interleave the transceiver channel placement of the Interlaken 100G IP when using Stratix V transceiver devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, you can interleave the transceiver channel placement of the Interlaken 100G IP when using Stratix® V transceiver devices within the following limitations.

Resolution

When implementing a x12 channel, 100G Interlaken IP, two x6 channel transceiver PHYs are instantiated inside the IP. Similarly, when implementing a x24 channel, 100G Interlaken IP, four x6 channel transceiver PHYs are instantiated inside the IP.

You can interleave the transceiver channel placement as long as you ensure that each logical group of 6 channels remain within a single physical transceiver block.

For instance, the following x12 channel placement would be illegal because logical lane 2 is placed in transceiver block 1 but lanes 0-1 and 3-5 are placed in transceiver block 0. Similarly, logical lane 11 is placed in transceiver block 0 but lanes 6-10 are placed in transceiver block 1.

Transceiver Block 1

GXB_[Tx,Rx]_[L,R][11] = Logical lane 2
GXB_[Tx,Rx]_[L,R][10] = Logical lane 8
GXB_[Tx,Rx]_[L,R][9] = Logical lane 9
GXB_[Tx,Rx]_[L,R][8] = Logical lane 10
GXB_[Tx,Rx]_[L,R][7] = Logical lane 6
GXB_[Tx,Rx]_[L,R][6] = Logical lane 7

Transceiver Block 0

GXB_[Tx,Rx]_[L,R][5] = Logical lane 5
GXB_[Tx,Rx]_[L,R][4] = Logical lane 11
GXB_[Tx,Rx]_[L,R][3] = Logical lane 3
GXB_[Tx,Rx]_[L,R][2] = Logical lane 4
GXB_[Tx,Rx]_[L,R][1] = Logical lane 0
GXB_[Tx,Rx]_[L,R][0] = Logical lane 1

The following would be a legal x12 channel interleaved channel placement because logical channels 0-5 all reside in transceiver block 0, and logical channels 6-11 all reside in transceiver block 1.

Transceiver Block 1

GXB_[Tx,Rx]_[L,R][11] = Logical lane 11
GXB_[Tx,Rx]_[L,R][10] = Logical lane 8
GXB_[Tx,Rx]_[L,R][9] = Logical lane 9
GXB_[Tx,Rx]_[L,R][8] = Logical lane 10
GXB_[Tx,Rx]_[L,R][7] = Logical lane 6
GXB_[Tx,Rx]_[L,R][6] = Logical lane 7

Transceiver Block 0

GXB_[Tx,Rx]_[L,R][5] = Logical lane 5
GXB_[Tx,Rx]_[L,R][4] = Logical lane 2
GXB_[Tx,Rx]_[L,R][3] = Logical lane 3
GXB_[Tx,Rx]_[L,R][2] = Logical lane 4
GXB_[Tx,Rx]_[L,R][1] = Logical lane 0
GXB_[Tx,Rx]_[L,R][0] = Logical lane 1

Related Products

This article applies to 4 products

Stratix® V FPGAs
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA