Device Family: Arria V GT, Arria V GX, Stratix V GT, Stratix V GX
Type: Answers
Area: Intellectual Property


Last Modified: January 29, 2015
Version Found: v11.1 Service Pack 2
IP Product: PCI Express 1/2/4/8 Lanes (x8)

Do I need to connect nPERST to my core design?

Description

Starting from the Stratix® V and Arria® V devices, nPERST dual-purpose pins were added, one for each quadrant in which a PCIe® core exists - device dependent.  This pin is used to bring the PCIe slot reset, PERST_N, into the device and connect to the cores pin_perst port.

Prior to Quartus® II software release 12.0, the connection of pin nPERST to pin_perst was not enforced.  When you migrate your design to Quartus II software release 12.0 or newer, Quartus will issue an error when this connection is not in place.

It is recommended that nPERST be used in your design and connected to the appropriate PCIe HIP's pin_perst port.

Workaround/Fix

In cases where you did not connect nPERST to pin_perst because of using an early version of Quartus II software, cannot add this because boards are complete, and are migrating to the Quartus 12.0 or newer, the workaround is:

  1. Open the PCIe HIP instance top-level file
    • Avalon-ST:  altpcie_sv_hip_ast_hwtcl
    • Avalon-MM:  altpice_sv_hip_avmm_hwtcl
  2. Must use Soft Reset Controller
    • Search for hip_hard_reset_hwtcl and set its value to \'0\' (zero) in the PCIe HIP instance top-level file
  3. Disable pin_perst input to the variant instance
    • Hardwire pin_perst to 1\'b1 in PCIe HIP instance top-level file
  4. Drive npor input with user_reset
    • Required by Soft Reset Controller
    • Used to reset the core and application logic
  5. Ensure that your Quartus II project points to the .qip file, not the .qsys file