Description
Due to a problem with the design examples, the following design variants will see underflow errors when tested with packets that are more than 4100 bytes long:
1) 10M/100M/1G/10G Ethernet Design Example
2) 1G/10G Ethernet Design Example
This error is caused by the size of the external FIFO buffer between the MAC and traffic controller. The size, 8 x 512 bytes, is too small, causing the Avalon-ST valid signals to be de-asserted during the frame transmission.
Impact
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Users will observe corrupted packets and CRC error reported by the packet monitor.
Resolution
To work around this problem, increase the depth of the external FIFO, altera_eth_fifo_tx and altera_eth_fifo_rx instances, by changing the DC_FIFO_DEPTH & SC_FIFO_DEPTH parameter values from 512 to 2048 in rtl/altera_eth_channel.sv.