When a Nios® II design is simulated using the flow from the Nios II Software Build Tools (SBT) for Eclipse, you will see uninitialized data returned from the external memory model for any instruction accesses and the program data will be returned from the memory controller to the Nios II processor.
When a Nios II simulation is started using the Nios II SBT, the memory controller is modified to add a alt_mem_if_avalon_dram_model module. This module is inserted at the Avalon®-MM slave interface of the UniPHY IP.
The model passes all Avalon-MM control signals through so that the controller timing is retained, but the readdata is replaced by readdata from the model. The model is initialised with data from the .elf file that was built within the Nios II SBT for Eclipse.
When a write is performed to the external memory the data is written to both the external memory and the internal alt_mem_if_avalon_dram_model.
For more information on simulating Nios II based designs, refer to AN351: Simulating Nios II Embedded Processor Designs (PDF).