You may experience this problem when using the UART (RS-232 Serial Port) component in a Qsys design with Quartus® II software version 11.0. This may result in the UART not synchronizing or communicating with the other end.
To work around this issue calculate the correct divisor_constant, by dividing the UART input clock frequency assigned to the UART, by the assigned Baud rate(bps), then verify this value is assigned to the divor_constant simulation varible in the Qsys generated <Qsys_system_name>_uart_0 file. If needed change the assigned value to match your calculation.
For example, the input clock to the Qsys UART is 83MHz. The assigned Baud rate(bps) = 115200. The divisor should be 83,000,000 / 115200 = 720. When verifying this value in the _uart_0 file you find the following lines of code:
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign divisor_constant = 434;
//synthesis read_comments_as_HDL off
Change the divor_constant = 720 as shown below.
// assign divisor_constant = 720;
This problem is fixed in Quartus II software version 11.0 SP1.