During Avalon master write bursts, the master port must assert constant values on address, byteenable (if present) and burstcount for the duration of the burst.
The Avalon Interface Specification incorrectly describes the behavior for address and burstcount during burst write transfers. The Avalon Interface Specification states: "The start of a write burst is similar to the start of a fundamental master write transfer. The master port asserts address, writedata, write, and byteenable (if present) in addition to burstcount. ... This is the only time that the Avalon switch fabric captures burstcount and address; the master port can de-assert them through the remainder of the burst." This description will be corrected in a future version of the document.
For additional information, see the Nios® II and SOPC Builder errata for version 6.0
http://www.altera.com/support/ip/processors/nios2/er/ips-niosii-er.html