Why does Qsys not port map the "chipselect", "write_n", and "writedata" signals to the PIO in my Qsys system?

This issue is specific to systems developed with Qsys, as SOPC Builder maps these signals correctly. 

The problem occurs when you configure the PIO (Parallel I/O) as input only, and configure it for "Edge capture register".  The edge capture mode requires a write to clear the edge detection signals and therefore, must have the "chipselect", "write_n", and "writedata" signals.

To work around this issue, enable Generate IRQ.  When using the Generate IRQ, the additional signals will be port mapped in the top level Qsys system.  This IRQ does not need to be connected in your system.

This issue is scheduled to be fixed in a future release of the Quartus® II software.