Description
The design examples for SerialLite II IP core on altera.com (http://www.altera.com/support/examples/interfaces-peripherals/exm-seriallite-stratix-v.html) are supported for verilog simulation only. You may encounter issues if you simulate the design examples in VHDL.
Resolution
No work around is provided. You must create your own VHDL simulation by referring to the existing Verilog HDL design examples on altera.com.