Article ID: 000084658 Content Type: Troubleshooting Last Reviewed: 06/02/2016

Why is the Arria 10 Hard IP for PCI Express Configuration Space register programming lost when downtraining from Gen3?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    A Surprise Link Down (SLD) event may occur for an Arria® 10 Hard IP for PCI Express® when changing speed from Gen3 to Gen1 or Gen3 to Gen2. This event occurs when the Arria 10 PCIe® Hard IP core is configured in Gen3 mode only.  When the SLD event occurs, the link goes to the Detect state and retrains. The PCIe bus must be re-enumerated after the link reaches L0. The rate of occurrence is low.

    Resolution This problem will be addressed in a future Quartus® Prime release.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices