Description
You must use the Hexadecimal (Intel-Format) File (.hex) memory initialization file format when simulating VHDL designs with a third-party simulator.
You must use either the RAM Initialization File (.rif) or HEX memory initialization file format when simulating Verilog HDL designs with a third-party simulator.
For detailed instructions, please refer the appropriate chapter in the Simulation section in Volume 3 of the Quartus II handbook.