Issue 136531: Clock Networks and PLLs in Stratix IV Devices, Version 3.4
Page 5-14, Notes to Figure 5-11. Note 2 currently states, for the Static Clock Select signals, that when the device is operating in user mode, you can only set the clock select signals through a configuration file (SRAM object file [.sof] or programmer object file [.pof] and this cannot be dynamically controlled.
Note 2 should state "You can only statically set the clock select signal through a configuration file (.sof or .pof)".
Issue 140213: DC and Switching Characteristics in Stratix IV Devices, Version 5.3
Table 1–42 indicates that for a -2/-2X speed grade Stratix IV Devices, 1600Mbps data rate is supported for source synchronous SERDES with True Differential I/O Standards. The maximum possible data rate achieved in the Stratix IV device source synchronous SERDES is design dependent. The source synchronous SERDES is implemented by using the ALTLVDS_RX and ALTLVDS_TX megafunctions. You can select the deserialization / serialization factor for your interface using these megafunctions. The Fmax specification for the SERDES is based on the fast clock used for the serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
Issue 156376: Clock Networks and PLLs in Stratix IV Devices, Version 3.4
There are two bullets for requirements when using automatic clock switchover, the first one is incorrect. It says:
"Both clock inputs must be running."
The purpose of automatic clock switchover is to switch between clocks if one stops running. The actual requirement is both clocks need to be running when the FPGA is configured. The bullet should say:
"Both clock inputs must be running when the FPGA is configured."
Issue 91332: Volume2, Chapter 1. Transceiver Architecture in Stratix IV Devices, Version 4.5
Page 1-152 incorrectly states:
Table 1–57 lists the typical configuration times for Stratix IV GX devices when configured using the Fast Passive Parallel (FPP) configuration scheme at 125 MHz.
But maximum configuration frequency in FPP depends on the device variant as shown in Volume1, Chapter 10, Table 10-4.
It should say:
Table 1–57 lists the typical configuration times for Stratix IV GX devices when configured using the Fast Passive Parallel (FPP) configuration scheme at the maximum frequency.
Issue 357589, DC and Switching Characteristics in Stratix IV Devices, version 4.6
Table 1-23 incorrectly implies that all PCI Express® Gen2 lane widths are supported in both commercial and industrial -3 devices.
As shown correctly in Table 1-9 of the PCI Express User Guide:
A Stratix® IV PCI Express Gen2x8 Interface requires -2 or -3I device speed grades (-3C does not support Gen2x8).
Issue 10006592: Volume 2, Chapter 1, Transceiver Architecture in Stratix IV Devices, Version 4.1
The "Modes of Operation of AEQ" section, of the Straitx IV Transceiver Architecture chapter explains that there are three modes of operation for AEQ where as only "One-time" mode is supported by Quartus® II Software.
Refer to Table 1-2 of the Addendum to the Stratix IV Device Handbook chapter for updates about 'Adaptive Equalization (AEQ)" feature in SIV transceivers.
Issue 10006412: Volume 1, Chapter 10, Configuration, Design Security, Remote System Upgrades in Stratix IV Devices, Version 3.1
The tCF2ST1(nCONFIG high to nSTATUS high) timing does not vary according to the tCFG (nCONFIG pulse width). After the nCONFIG is released high, the nSTATUS is released high within the tCF2ST1 maximum specification provided you do not hold the nSTATUS low externally.
The note associated with the respective table will be changed to say "This value is applicable if you do not delay configuration by externally holding the nSTATUS low."
Issue 10006465: Volume 4, Chapter 1, DC and Switching Characteristics, Version 4.3
In the notes to Table 1-5 it states that "Altera recommends a 3.0V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile security key, you may connect the VCCBAT to either GND or a 3.0V power supply."
This note will be updated to state "Altera recommends a 3.0V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile security key, you may connect the VCCBAT to either GND or a 1.2V-3.3V power supply."
Resolved issues:
Issue 360127, DC and Switching Characteristics in Stratix IV Devices, version 5.0
Table 1-22 is missing the LVDS receiver voltage input range.
When Dmax > 700 Mbps, the LVDS input voltage requirement is 1.0 V <=VIN <=1.6 V.
When Dmax <= 700 Mbps, the LVDS input voltage requirement is zero V <=VIN <=1.85 V.
Issue 35430: DC and Switching Characteristics in Stratix IV Devices, Version 5.3
Table 1-42 in the DC and Switching Characteristics for Stratix IV Devices states that for a -2/-2X speed grade device, 800MHz is supported for fHSCLK_in (input clock frequency) True Differential I/O Standards. This does not apply to 680, 530, 360 and 290 density devices. The specs for such parts are de-rated by 5%. The correct frequency should be 762MHz for these devices.
Issue 35430: DC and Switching Characteristics in Stratix IV Devices, Version 5.2
Table 1-22 indicates VCCIO is used for differential standards for I/O operation. This is not correct. VCCIO is used for differential output operation. The following details clarify the power pins which are used for differential input operations:
- Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins.
- Differential clock inputs in column I/O are powered by VCC_CLKIN which requires 2.5 V. Differential inputs that are not on clock pins in column I/O are powered by VCCPD which requires 2.5 V. All differential inputs in row I/O banks are powered by VCCPD which requires 2.5V.
Issue 10006109: Volume-2, Chapter-1, Version 4.1
Page 1-149 states, “If you use the Stratix IV GX and GT PCI Express hard IP block, assert the testin[5] port of the PCI Express Compiler-generated wrapper file in your design. Asserting this port forces the LTSSM within the hard IP block to transition to these states. The testin[5] port must be asserted for a minimum of 16 ns and less than 24 ms.”
It would be incorrect to assert testing[5] port. test_in[6] port should be asserted, instead of testin[5] port.
Issue 10005907: Volume 2, Chapter 1, Version 4.1
Page 1–188 states that PCI Express (PIPE) Reverse Parallel Loopback feature is not supported in Stratix IV GT devices. This is incorrect. It is supported in Stratix IV GT devices.
Issue 10005786: Stratix IV handbook, Volume-1,2,3 and 4, Version 4.0
The minimum data rate supported by Stratix® IV GT device is 600Mbps, instead of 2.488Gbps.
Issue 10005787: Volume 2 Chapter 1 "Stratix IV Transceiver Architecture" Version 4.0
Table 1-70. The CMU PLL of Stratix IV GT support 600Mbps to 11.3Gbps data rates.
Issue 10005409, Volume-2, Chapter-2, Version 4.0
Table 2-4, Note (1) in the device handbook states,"When configured as HCSL, the Quartus® II software automatically selects the DC coupling with external termination option for the refclk pins signal." Following additional steps are actually needed in Quartus® II software to enable DC coupling/external termination on the REFCLK pins.
1. Add the following assignment to your project .qsf file
set_instance_assignment -name INPUT_TERMINATION OFF -to <refclk_pin_name>
2. Re-compile the design
Issue 10005661, Volume-2, Chapter-5 ver 4.0. Table 5–15. EyeQ Interface Register Mapping
The statement, " Bit [1]—Read/Write: Writing a 1 to this bit writes the contents of the data register to one of the EyeQ registers depending on the address stored in the EyeQ register address register. Writing a 0 reads the contents of the EyeQ register." is incorrect.
It should read, " Bit [1]—Read/Write: Writing a 0 to this bit writes the contents of the data register to one of the EyeQ registers depending on the address stored in the EyeQ register address register. Writing a 1 reads the contents of the EyeQ register."
Issue 366739, DC and Switching Characteristics in Stratix IV Devices, version 4.6
Note (4) under Table 1-6 states, "VCCH_GXBL/R must be connected to a 1.4-V supply if the transmitter channel data rate is > 6.25 Gbps." Data rate limit of ">6.25 Gbps" is incorrect. It should state ">6.5 Gbps".
Issue: 10006605, DC and Switching Characteristics in Stratix IV Devices, version 4.4.
VCCPT was removed from tables 1-1 and 1-5 by mistake. The recommended specification for VCCPT is 1.5V.
Issue: 10006694: Hot Socketing and Power-On Reset in Stratix IV Devices, version 3.1.
There are pointers in this chapter that states "Altera recommends powering up VCC before VCCAUX." but should read "Altera requires powering up VCC before VCCAUX."
Issue: 10006604, DC and Switching Characteristics in Stratix IV Devices, version 4.4.
VCCCB was added to tables 1-1 and 1-5 by mistake.
Issue 10005417, Volume-2, Chapter-5 "EyeQ" Version 3.0
The statement, "When you enable the EyeQ hardware, it allows the CDR to sample across 64 different positions within two unit intervals (UIs) of the incoming data. You can manually control the sampling points and check the bit-error rate (BER) at each of these 64 sampling points." is incorrect.
It should read, "When you enable the EyeQ hardware, it allows the CDR to sample across 32 different positions within one unit intervals (UIs) of the incoming data. You can manually control the sampling points and check the bit-error rate (BER) at each of these 32 sampling points."
Issue 10006578, Vol. 1, Ch 3: TriMatrix Memory Blocks in Stratix IV Devices, Version 3.1
The Stratix IV handbook describes the M9K and M144K memory cells as being initialized to all 0\'s upon power up unless there is a mif file specified.
Issue 10003993, Volume 4, Chapter 1 "DC and Switching Characteristics" Version 3.1
Table 1-37 (table 1-36 in version 4.0) has been corrected to show the data rates for SERDES factor J=2 using DDIO registers.
Issue 10003562, Volume 1, Chapter 12 "JTAG Boundary-Scan Testing in Stratix IV Devices" Version 2.0
Version 3.0 updated Table 12-2 with the correct 16-bit Part Number in the 32-bit IDCODE for the EP4SGX230 device.
Issue 10003555, Volume 4, Chapter 1 "DC and Switching Characteristics" Version 2.1
The electical specifications for LVPECL in Table 1-18 (Table 1-21 in version 4.0) apply to both row and column input clock pins.
Issue 10003397, Volume 4, Chapter 1 "DC and Switching Characteristics" Version 2.1
The Iout specification has been added to Table 1-1.
Issue 10003232, Volume 2, Chapter 3 "Configuring Multiple Protocols and Data Rates in aTransceiver block" Version 2.0
Table 3-7 shows the transceiver channels that are available when PCI Express hard IP block is enabled.Under the Ch1 column, the second row item shows the channel as available for utilization (indicated by \'avail\'). This information is incorrect. Therefore, for a PCI x1 link with 2 virtual channels, Ch1 cannot be used for any configuration.
Issue 10003061, Volume 2, Chapter 1 "Stratix IV Transceiver Architecture" Version 1.0
Details regarding the Byte Ordering Block and Figures 1-92 and 1-93 were updated in revision 2.0.
Issue 10002468, Volume 4 Chapter 1 "DC and Switching Characteristics" Version 1.0
The minimum voltage for VCCD_PLL was corrected in version 2.0.
Issue 10003439, Volume 1 Chapter 1 "Stratix IV Device Family Overview " Version 1.0
Table 1-1 was updated in revision 2.1 with the correct number of PCI Express Hard IP blocks for the EP4SGX530 device.
Issue 10006590, Vol. 2, Ch 5: Stratix IV Dynamic Reconfiguration, Version 4.1
The "Adaptive Equalization (AEQ)" section, page 5-74, of the Straitx IV Dynamic Reconfiguration chapter explains that there are three modes of operation for AEQ where as only "One-time" mode is supported by Quartus® II Software.
Please refer to Table 1-2 of the Addendum to the Stratix IV Device Handbook chapter for updates about \'Adaptive Equalization (AEQ)" feature in SIV transceivers.