Device Family: Arria V GT, Arria V GX, Arria V ST, Arria V SX, Stratix V E, Stratix V GS, Stratix V GT, Stratix V GX
Type: Answers
Area: Component

Last Modified: October 01, 2015
Version Found: v12.0
Version Fixed: v12.0 Service Pack 1

Warning (205007): Truncated pin name "sstl15i_crio_g50c_r50s1" in IBIS Output File to "sstl15i_crio_g50c_r5" to comply with IBIS 3.2/4.0/4.1 standard


Due to a problem in the Quartus® II software version 12.0, you may see this warning when generating IBIS models for Stratix® V and Arria® V devices. This warning may occur if the following conditions are true:

  • The design contains bidirectional pins with calibrated parallel on-chip termination (OCT) enabled
  • You have turned on the Enable model selector option on the EDA Tool Settings:Board-Level category of the Settings dialog box
  • Due to this problem, the EDA Netlist Writer adds the calibrated parallel OCT naming convention to the names of the generated IBIS models on bidirectional pins. This longer name exceeds the character limit allowed by the IBIS specification through version 4.1. Additionally, the output model is corrupt and does not pass the IBIS syntax check. The simulation results are not correct when using affected models.

    Altera does not support bidirectional models with parallel OCT. Affected models have either of the following strings in their name:

    • crio_g50c
  • ctio_g50c
  • Altera supports only input models with parallel OCT. Correct models have one of the following strings in their name:

    • cin_g50c
    • crin_g50c
    • ctin_g50c


    To generate correct IBIS models for Stratix V and Arria V devices in the Quartus II software version 12.0 for designs that use parallel OCT on bidirectional pins, turn off the Enable model selector option. Turning off this option allows the EDA Netlist Writer to generate IBIS models for bidirectional pins that have correct output buffer behavior.

    Additionally, if your design uses parallel OCT only on bidirectional pins and not on input-only pins, perform either of the following steps to generate the input parallel OCT model:

    • Create a test input pin in the top level of the design. Assign the desired I/O standard and input termination to the test input pin and compile the project. Because the EDA Netlist Writer only generates the output buffer model on bidirectional pins, adding an input-only pin is required to generate the input parallel OCT model.
    • Alternatively, create a simple test project with an input-only pin and assign the desired I/O standard and input termination to generate the parallel OCT model.

    This problem is fixed in the Quartus II software version 12.0sp1.