There are two causes for this issue:
I. If you have established an STDIO connection with a Nios II system via the nios2-terminal utility and then reset the FPGA or re-configure the FPGA, garbled data will appear. This is due to the nios2-terminal utility losing its connection with the JTAG logic in the FPGA (which is cleared when the FPGA is reset or reconfigured). To work around the issue, terminate the nios2-terminal session before resetting or reconfiguring the FPGA.
II. When connecting to the Nios II factory-safe example design (starting the nios2-terminal utility), garbled data may also be displayed. This is a known issue and will be corrected in Nios II 1.01, and is specific to this software example design. To work around the issue, connect via nios2-terminal using the following sequence of steps:
- Open the Nios II SDK shell from the Nios II folder of your start menu
- Open a second Nios II SDK shell
- If necessary, reset the development board to load the factory-safe design by pressing the "Force Safe" button.
- In the first SDK shell window, reset the Nios II processor by typing: "nios2-download --reset-target"
- In the second SDK shell window, type "nios2-terminal" to start the terminal application used for STDIO communication with the JTAG UART on the factory-safe design.
- In the first SDK shell window, direct the CPU to begin execution of the design by typing: "nios2-download --go"
At this point, the SDK shell window with nios2-terminal should be connected to the target without any garbled data to allow STDIO communication.