Device Family: Stratix III
Type: Answers
Area: Component


Last Modified: December 04, 2016

Are there known issues regarding the Stratix III Error Detection CRC feature that may result in incorrect MLAB operation?

Description

Yes, when the Error Detection (ED) CRC feature is enabled, it may cause the MLAB RAM blocks to operate incorrectly in Stratix® III devices. Only write operations in MLAB RAM blocks are affected. MLAB ROM blocks are not affected by this issue.

The ED CRC feature itself and CRC error flag operate correctly as expected. FPGA configuration bits are not affected by this issue.

Follow the recommended flow in Figure 1 to identify if your design is affected and to work around the problem.

Figure 1. Recommended Design Flow

Figure 1

For details on determining whether your design is affected and how to work around the problem, refer to Detailed Solution for Stratix III Error Detection (ED) CRC MLAB Issue (PDF).

You can download the script, patch, and related readme files using the links below: