Article ID: 000081824 Content Type: Product Information & Documentation Last Reviewed: 01/08/2016

How to manually instantiate the hard input FIFO from ALTDQ_DQS2 in Stratix V?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    For designs in Stratix® V devices using the ALTDQ_DQS2 megafunction with hard input FIFO enabled, there is a known issue where the hard input FIFO is not instantiated correctly. When enabling hard input FIFO, take note of the following: 

     

    1.   You must instantiate both “stratixv_read_fifo” and “stratixv_read_fifo_read_enable” blocks as per the UniPHY implementation

    2.   Some edits are required for “altdq_dqs2_stratixv_<design_file_name>.sv”, otherwise you will get the following fitter error during compilation:

     

                Error (175001): Could not place DQS Logic Block – Dynamic OCT Control Path fed by DQS I/O pad

    Resolution

    Contact Altera® Support for details regarding the “stratixv_read_fifo” and “stratixv_read_fifo_read_enable” blocks as well as the changes required in the “altdq_dqs2_stratixv_<design_file_name>.sv” file.

    This issue will be fixed in a future version of the Quartus® II software.

    Related Products

    This article applies to 5 products

    Stratix® V FPGAs
    Stratix® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V GS FPGA
    Stratix® V E FPGA