Article ID: 000081106 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Will local_rdata_valid be asserted when DQS edge is missing due to OCT timing issue reported in solution rd01212009_111?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, local_rdata_valid signal will be asserted as this is controlled and calculated by the controller based on the read and write latency and controller latency.

Related Products

This article applies to 1 products

Stratix® II GX FPGA