Article ID: 000085313 Content Type: Troubleshooting Last Reviewed: 03/17/2023

What output clock should I connect to the Native PHY Intel FPGA IP when using a fPLL as a transceiver TX PLL on Stratix® V, Arria® V, and Cyclone® V transceiver devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The output clock used to connect to the Native PHY Intel® FPGA IP when using a fPLL as a transceiver TX PLL on Stratix® V, Arria® V, and Cyclone® V transceiver devices will vary depending on whether dynamic reconfiguration of the fPLL is enabled or not.

Resolution

When dynamic reconfiguration of the fPLL is not enabled, you must connect the fPLL 'outclk_0' port to the Native PHY 'ext_pll_clk' port.

When dynamic reconfiguration of the fPLL is enabled, you must connect to fPLL 'phout[0]' port to the Native PHY 'ext_pll_clk' port. The 'phout' port is enabled by selecting the "Enable access to PLL DPA output port" option of the PLL parameter editor "Settings" tab.

Related Products

This article applies to 9 products

Stratix® V FPGAs
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V GT FPGA

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