You may see this error with SOPC Builder or Qsys when custom component has two or more interrupt interface signals and only one addressable interface, such as Avalon-MM slave interface, because each interrupt senders must be associated with indivisual addressable interface.
To prevent this error, the custom component design should be modified by following the steps below if the custom component has only one addressable interface such as Avalon-MM slave interface.
For example,
- The interrupt signals are OR'ed internally, and the custom component has only one interrupt interface signal associated with addressable interface.
- The interrupt signal is connected to CPU via IRQ setting on the System Contents tab in SOPC Builder or Qsys.
- The custom component has memory-mapped register corresponding to each interrupt signals.
(In addition, software should work as following.) - After CPU receives as interrupt from the custom component, CPU accesses to the memory-mapped register in the custom component to know which interrupt is caused.
- Subsequently, CPU might clear the corresponding register/bit to clear the interrupt.