Article ID: 000079728 Content Type: Troubleshooting Last Reviewed: 07/28/2015

Why is my HPS qspi clock interface inverted?

Environment

  • Quartus® II Subscription Edition
  • Clock
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The SoC Hardware Library (HWLIB) configures and controls the SoC Quad Serial Peripheral Interface (SPI) Controllers. The QSPI HWLIB source, can be found in the /ip/altera/hps/altera_hps/hwlib/include/alt_qspi.h file. 

    In SOC EDS 15.0 and earlier, the definition of the polarity ALT_QSPI_CLK_POLARITY_LOW and ALT_QSPI_CLK_POLARITY_HIGH and their respective values in alt_qspi.h is incorrect. 

    Resolution

    To work around this problem, edit alt_qspi.h and replace:
    ALT_QSPI_CLK_POLARITY_LOW     = 0

    with
    ALT_QSPI_CLK_POLARITY_LOW     = 1


    and


    ALT_QSPI_CLK_POLARITY_HIGH    = 1

    with
    ALT_QSPI_CLK_POLARITY_ HIGH   = 0

    This problem is scheduled be fixed in a future version of the Altera SoC Embedded Design Suite.

     

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices