Last Modified: November 03, 2014
Version Found: v14.0 Arria 10 Edition
pipe_hclkoutput clocks are incorrectly constrained in the PIPE designs in the Quartus® II Software version 14.0 Arria® 10 Edition.
To fix this problem, in your top level Synopsys Design Constraints (.SDC) file, follow these steps:
- Include the derive_pll_clock constraint in your SDC file.
- In a line beneath the derive_pll_clock constraint, use the remove_clock constraint to remove
- Recreate these clocks at their interfaces using the create_clock SDC command
This is scheduled to be fixed in a future version of the Quartus II software.