Article ID: 000074660 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why am I getting invalid data read back through the SPI Slave to Avalon Master Bridge core?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

This is a known issue with the SPI Slave to Avalon Master bridge core in Quartus II software version 11.x. The issue can occur when burst reads are performed to an Avalon slave that takes many cycles to respond. In this scenario, depending on the frequency relationship between the SPI and Avalon clocks, it is possible for one of the read-back data bytes to be incorrectly replaced with a NoOp word output to the SPI interface. The issue has only been seen with burst reads from the Avalon bus. To work around the issue, only perform single reads via the bridge to the Avalon bus. Write transactions are not affected.

This issue will be fixed in a future release of the Quartus II software.

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Intel® Programmable Devices