Article ID: 000085404 Content Type: Troubleshooting Last Reviewed: 08/22/2023

What is the purpose of the HPS SoC out1_n and out2_n signals?

Environment

  • Quartus® II Subscription Edition
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    Description

    When routing the output of the HPS UART to the FPGA, extra signals (out1_n and out2_n) are generated.  Due to a problem, the functionality of out1_n and out2_n is not described in the device handbook

    Resolution

    These two signals, out1_n, and out2_n, are user-designated outputs and can be set to an active low by programming the OUT1 or OUT2 bit of the MODEM Control Register to a high level.  A Master Reset operation sets this signal to its inactive (high) state.

    This information is added starting with release 15.1 of the device handbook.

    Related Products

    This article applies to 4 products

    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

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