Description
The JTAG UART can become unstable if the DEV_CLRn pin on the FPGA input has been assigned (in Quartus® II software) to generate a device-wide reset, and the FPGA is reset while the JTAG UART is active.
To workaround this problem, do not use the DEV_CLRn function in designs with the JTAG UART. Turn off the Enable device wide reset (DEV_CLRn) setting in Quartus II software.