Due to a problem in the automatically generated synopsys design constraints for the Arria® V/Cyclone® V Hard Processor System IP you may see this warning durng compilation or timing analysis.
The problem is caused by incorrect assignment order within the hps_sdram_p0.sdc file.
To workaround this problem you can modify the following lines the hps_sdram_p0.sdc file.
From:
# This is the CK clock
foreach { ck_pin } {
set_clock_uncertainty -to [ get_clocks ] (WL_JITTER)
create_generated_clock -multiply_by 1 -source -master_clock "" -name
}
# This is the CK#clock
foreach { ckn_pin } {
set_clock_uncertainty -to [ get_clocks ] (WL_JITTER)
create_generated_clock -multiply_by 1 -invert -source -master_clock "" -name
}
To:
# This is the CK clock
foreach { ck_pin } {
create_generated_clock -multiply_by 1 -source -master_clock "" -name
set_clock_uncertainty -to [ get_clocks ] (WL_JITTER)
}
# This is the CK#clock
foreach { ckn_pin } {
create_generated_clock -multiply_by 1 -invert -source -master_clock "" -name
set_clock_uncertainty -to [ get_clocks ] (WL_JITTER)
}
This problem is scheduled to be resolved in a future release of the Quartus® II software.