Article ID: 000085456 Content Type: Install & Setup Last Reviewed: 08/18/2023

Why does my 1G/10G or 10GBASE-KR PHY design fail Link Training in Verilog HDL simulation?

Environment

  • Quartus® II Subscription Edition
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in Quartus® II software version 14.0 Intel® Arria® 10 Edition, you may see the following (or similar) warnings in simulation when Link Training is enabled.

    "Warning: (vsim-3533) [FOFIW] - Failed to open file

    'USER_QUARTUS_INSTALLATION_PATH/acds/quartus/../ip/altera/alt_xcvr/altera_xcvr_10gbase_kr/arria10/

    cpu/kra10_cpu_imem.ver' for writing."

    Following these warnings, Link Training will fail.

    Resolution

    To workaround this problem, perform the following steps:

    1. Navigate to the directory in which the IP was generated:

    <USER_IP_GENERATION_DIR>/altera_avalon_onchip_memory2_140/sim/

    2. Within this directory, locate 2 Verilog HDL files with names similar to that shown below:

    krip_altera_avalon_onchip_memory2_140_<RANDOM_CHARACTERS>.v

    3. Locate the following parameter line similar to the following in each of the files from above:

    parameter INIT_FILE = "/USER_QUARTUS_INSTALLATION_PATH/acds/quartus/../ip/altera/alt_xcvr/

    altera_xcvr_10gbase_kr/arria10/cpu/kra10_cpu_imem.hex";

    4.) Change each parameter to:

    parameter INIT_FILE="kra10_cpu_Xmem.hex";

     

    Related Products

    This article applies to 4 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA