Article ID: 000075653 Content Type: Error Messages Last Reviewed: 09/12/2014

Error: PLL Output Counter parameter 'output_clock_frequency' is set to an illegal value of <clock frequency> on node gpll~PLL_OUTPUT_COUNTER'

Environment

  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may get this error in the Quartus® II software when the Device Speed Grade chosen in the Altera Phase-Locked Loop (Altera PLL) IP Core MegaCore® does not match the speed grade of your target Stratix® V, Arria® V or Cyclone® V device.

    Resolution Ensure the Device Speed Grade chosen in the Altera PLL IP Core MegaCore matches the speed grade of your target device.

    Related Products

    This article applies to 18 products

    Arria® V GZ FPGA
    Cyclone® V SX SoC FPGA
    Stratix® V FPGAs
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V FPGAs and SoC FPGAs
    Arria® V GT FPGA
    Arria® V SX SoC FPGA
    Cyclone® V FPGAs and SoC FPGAs
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA

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