The definitions of the dedicated transceiver refclk pin XCVR_REFCLK_PIN_TERMINATION QSF assignments for Stratix® V, Arria® V, and Cyclone® V transceiver devices are detailed below.
This assignment is the default dedicated transceiver reference clock pin setting and is recommended for all transceiver designs. This setting should be used with AC coupled signals. This setting implements on-chip termination and on-chip signal biasing.
This assignment should be used when the dedicated transceiver reference clock pins are fed by a DC coupled signal whose Vcm meets the device specification. This assignment implements internal on-chip termination but not on-chip signal biasing.
This assignment should be used when the dedicated transceiver reference clock pins are fed by a DC coupled signal. This option does not implement internal on-chip termination or signal biasing. You must implement termination and signal biasing to the appropriate device Vcm outside of the FPGA. This assignment is recommended for PCI Express compliance and the HCSL IO Standard.
Electrical specifications for dedicated transceiver refclk pins can be found in the appropriate Stratix V GX, Arria V GX, and Cyclone V GX device datasheets.