Article ID: 000083430 Content Type: Error Messages Last Reviewed: 01/03/2023

Error (175020): Illegal constraint of LVDS_CHANNEL that is part of Altera LVDS SERDES

Environment

  • Intel® Quartus® Prime Design Software
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You will receive this error if you are using Altera LVDS SERDES IP in Rx-CDR mode, with certain pin constraints in Arria® 10 and Cyclone® 10 GX devices.

    The Altera LVDS SERDES IP in Rx-CDR mode may only be placed on dedicated even numbered channels. 

    Resolution

    To identify which pins may be used in Rx-CDR mode, refer to your device's Dedicated Tx/Rx Channel column of the pinout file. Only pin pairs with even numbers may be used.  For example, LVDS2K_1 may not be used, and LVDS2K_2 can be used.

    Related Products

    This article applies to 5 products

    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 SX SoC FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 GX FPGA