You will see the following warning in the Quartus® II fitter report if a PLL does not have a compensated clock specified:
Warning (177007): PLL(s) placed in location <PLL location> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
Info (177008): <instance_name> altera_pll:altera_pll_i|general.gpll~FRACTIONAL_PLL
The way to specify a compensated clock target (which can be done directly in the ALTPLL megafunction GUI), is to make a “Match PLL Compensation Clock” assignment. The syntax of the PLL clock node has to be specific in order for it to be saved in the Assignment Editor. Filter on *outclk_wire* in a post compilation filter in the node finder.
Where outclk_wire corresponds to C0 in the Altera_PLL instance.