The ALTLVDS_RX megafunction provides a limited drop-down list selection for setting the clock and data relationship in non-DPA mode. The parameter is What is the phase alignment of 'rx_in' with respect to 'rx_inclock'. By setting this parameter, the ALTLVDS_RX megafunction calculates the proper capture phase for the serial data.
The phase shift values are based on the rx_inclock period, which can vary depending on your interface. The following are common rx_inclock usage scenarios:
- One rx_inclock period for all of the serial bits per word (single data rate clock)
- Two rx_inclock periods for all of the serial bits per word (double data rate clock)
- Equal number of rx_inclock periods for all of the serial bits per word (full data rate clock)
The available phase shift selections in the megafunction sets the capture clock to different positions in the serial data. This is based on the number of rx_inclock periods for the number of serial bits per word (deserialization factor). The ability for you to specify the phase shift within a single data bit period depends on how many rx_inclock periods occur for each serial word received.
For example, consider an interface with the following parameters:
- Data rate = 800 Mbps
- Deserialization factor = 8
- rx_inclock = 100 MHz
In this case, there is one rx_inclock period for all 8 serial bits received. Thus, each setting you choose that are in 45 degree increments in the ALTLVDS_RX megafunction (0, 45, 90 degrees, etc) sets the capture phase at a different bit position in the serial word. This setting will not change the phase capture position within a bit period. Each of these selections results in a different word alignment on the parallel side of the interface.
Consider a second example with the following parameters:
- Data rate = 800 Mbps
- Deserialization factor = 8
- rx_inclock = 800 MHz
In this case, there is one rx_inclock period for each serial bit period. Each setting you choose will change the capture phase within a single bit period.
There may be cases where you want to set the capture phase at a position that is not possible using the ALTLVDS_RX megafunction drop-down list selection for the What is the phase alignment of 'rx_in' with respect to 'rx_inclock' parameter.
The total possible number of capture phase positions depends on the deserialization factor of the interface. For each serial bit period, there are 8 phases available from the fast clock. The fast clock operates at the serial bit rate.
The total number of possible capture phases is equal to 8 * deserialization factor.
In the examples above, the deserialization factor is 8, so there are a total of 64 available phase positions to set the capture clock across all 8 bits of the serial word. You can choose to set the capture phase within a single bit position, at different bit positions, or a combination of both by modifying the ALTLVDS_RX variation file.
Legal phase values must be in increments equal to the fast clock period divided by 8. Every 8 phase shift increments are equal to one bit period. Using the parameters from Example 1 above, if you wish to specify the rising edge of rx_inclock to be center aligned on the third serial bit of the 8 bit word, you would need a total of 20 phase shift increments (8 phase increments for each of the first two bit periods, plus 4 phase increments for the center aligned rising edge in the third bit period).
The fast clock in this example operates at 800 MHz, the same as the data rate. The fast clock period is 1.25 ns, which results in 156.25 ps per phase shift increment. The total required phase shift in this example to describe the input clock and data relationship is 20 * 156.25 ps = 3.125 ns.
Once you calculate the desired phase shift value, enter it in the ALTLVDS_RX variation file. Open the file and locate the following parameter:
For Verilog: ALTLVDS_RX_component.inclock_phase_shift
For VHDL: inclock_phase_shift
Enter the value you calculated, the units are picoseconds.
Note: The most significant bit (MSB) of the serial data may not be the MSB of the deserialized parallel data on the rx_out port of the ALTLVDS_RX megafunction. You are required to use the bitslip circuit to set the word boundary on the parallel side.
For more information, refer to the Aligning the Word Boundaries section of the LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunctions User Guide (PDF).