The DMA controller available in SOPC Builder will stall if either the source or destination components assert waitrequest causing the FIFO in the DMA controller to reach an empty or full status. There is also a known issue when the DMA performs reads from low latency component such as SSRAM or on-chip memory. The internal latency of the DMA controller is sometimes greater than the read latency of the component connected to the DMA read master, causing the transfer throughput to degrade.
This issue occurs when the component connected to the DMA read master has a latency of 0-3 clock cycles. To improve the transfer throughput increase the read latency of the component connected to the DMA read master. If the component does not have a read latency setting, you can increase the latency by inserting pipeline bridges between the DMA read master and the component. Pipeline bridges can be chained together to add more than one clock cycle of read latency to a component.
When adding the pipeline bridge(s) it is recommended to set the bridge slave address to 0x0. This will prevent the address space of your system from changing. To increase the read latency of a component connected to the tri-state bridge you can enable additional registering in the tri-state bridge settings which increases the read latency by one clock cycle.