Description
This error may occur in the Quartus® II software version 9.0, if Physical Synthesis optimizations are enabled for your project and your design contains a PLL with an illegal reference clock connection.
To work around this problem, follow these steps:
- Disable Physical Synthesis optimizations for your project and recompile your design.
- Examine your Analysis & Synthesis report to identify any PLLs with illegal reference clock connections.
- Fix these connectivity errors and recompile your design.
- After you have fixed the illegal connections, you can enable Physical Synthesis optimizations again for your Quartus II project.
This problem is scheduled to be fixed in a future version of the Quartus II software.