Device Family: Stratix IV GX
Type: Answers
Area: Intellectual Property


Last Modified: September 11, 2012
IP Product: POSPHY Level 4 (SPI 4.2)

Can PLLs for TX and RX be shared using the SPI 4.2 core in Stratix IV GX ES devices?

Description

Yes, PLLs can be shared using the Altera® SPI 4.2 MegaCore® function in Stratix® IV GX devices. PLL sharing with the SPI 4.2 core between transmit (TX) and receive (RX) is more complicated for Stratix IV GX ES than other FPGA devices.

The SPI 4.2 core's ALTLVDS Megafunction for Stratix IV GX ES does not support internal sharing of PLL for Tx and Rx. DPA misallignment takes significantly longer than expected time to select the optimum phase. This will cause non-ideal phase and resulting in data bit errors even after the DPA lock signal has been asserted. Resetting the DPA circuit also trigger this problem.

To enable PLL sharing, please follow the below step by step settings :

    1.  Check "Use External PLL" in the Parameter Settings tab of the ALTLVDS Megafunction

    2.  Uncheck "Use shared PLL(s) for receivers and transmitters" in the Frequency/PLL settings tab of the ALTLVDS Megafunction

    3.  Check "Enable PLL calibration" in the 3rd DPA settings tab of the ALTLVDS Megafunction

    4.  Execute Megawizard plug in manager and create an ALTPLL Megafunction. Apply the appropriate device speed grade and clock input frequency according to the system configuration. Choose Left_Right PLL

    4-1.  In the PLL Reconfiguration tab, under Dynamic phase configuration, select "Create optional inputs for dynamic phase reconfiguration"

    4-2.  In the Output Clocks tab - clk c0, enter the output clock frequency (the fast clock running at LVDS data rate). This clock will feed rx_inclock and tx_inclock. Set phase shift = -180 degrees with respect to VCO clock. Set Duty Cycle to 50%. Select "use these clock settings for the DPA clock"

    4-3.   In the Output Clocks tab - clk c1, enter the ouput clock frequency (fast clock / deserialization factor). Feed this clock output to tx_enable and rx_enable. Set phase shift to [(deserialization factor - 2) / deserialization factor] * 360 degrees. Set Duty Cycle to (100 / deserialization factor)

   4-4.   In the Output Clocks tab - clk c2, enter the output clock frequency (fast clock / deserialization factor). Feed this clock output to rx_syncclock. Set phase shift to (-180 degress / deserialization factor). Set Duty cycle to 50%

Figure 1 

Figure 1 PLL to LVDS Clocking Scheme

    5.   Make changes to the SPI4.2 Rx core modules

    5-1.  In <SPI4 variation name>_rx_core.v, replace the instantiation of  <SPI4 variation name>_rx_data_phy_altlvds with the instantiation below : 

<SPI4 variation name>_rx_data_phy_altlvds rx_data_phy_altlvds (

.pll_areset(pll_areset),
.pll_phasedone(phasedone),
.rx_cda_reset({lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset}),
.rx_channel_data_align(bitslip),
.rx_enable(rx_enable),
.rx_fifo_reset({lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset}),
.rx_in(rx_in),
.rx_inclock(rx_inclock),
.rx_reset({lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset, lvds_reset}), // input [16:0],
.rx_syncclock(rx_syncclock),
.dpa_pll_cal_busy(dpa_pll_cal_busy),
.pll_phasecounterselect(phasecounterselect),
.pll_phasestep(phasestep),
.pll_phaseupdown(phaseupdown),
.pll_scanclk(scanclk),
.rx_dpa_locked(stat_rd_dpa_lvds_locked),
.rx_out(rx_out_serdes)  );

    5-2. In <SPI4 variation name >.v ( SPI4.2 Rx core wrapper), include the following instantiation:

<SPI4 variation name>_pl4_rx_core   <SPI4 variation name>_pl4_rx_core_inst (

...

  .rx_inclock(rx_inclock),
  .rx_enable(rx_enable),
  .rx_syncclock(rx_syncclock),
  .dpa_pll_cal_busy(dpa_pll_cal_busy),
  .phasecounterselect(phasecounterselect),
  .phasestep(phasestep),
  .phaseupdown(phaseupdown),
  .scanclk(scanclk),
  .phasedone(phasedone),

...);

    6.  Make changes to SPI4.2 Tx core module :

    6-1.  In <SPI4 variation name>_tx_core.v, replace the instantiation of  <SPI4 variation name>_tx_data_phy_altlvds with the instantiation below : 

<SPI4.2 variation name>_tx_data_phy_altlvds tx_data_phy_altlvds (

 .tx_enable(tx_enable), //input
 .tx_in(tx_in_i),     //input
 .tx_inclock(tx_inclock),//input
 .tx_coreclk(tx_coreclk),
 .tx_out(tx_out), //output
 .tx_outclock(tx_outclock) //output );

    6-2.  In <SPI4 variation name >.v ( SPI4.2 Tx core wrapper), include the following instantiation :

<SPI4.2 variation name>_pl4_tx_core  <SPI4.2 variation name>_pl4_tx_core_inst (

...

  .trefclk(trefclk),
  .tx_enable(tx_enable),
  .tx_coreclk(tx_coreclk),

... );

    7.  The SPI4.2 receiver ALTLVDS rx_out bus output be registered with rx_outclock.

    8.  The SPI4.2 transmitter ALTLVDS tx_in bus be pre-registered with tx_coreclock.

    9.  Invert the shared PLL lock output and feed it to pll_areset port of the ALTLVDS Megafunction.