Article ID: 000078866 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is offset cancellation triggered every time the reconfig_reset signal is asserted in Cyclone IV GX devices?

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Description

Due to a problem in the Quartus® II software versions 10.0 and 10.1, some unexpected behaviors are observed during receiver offset cancellation process.

1. Offset cancellation is triggered every time the reconfig_reset signal is asserted in Cyclone® IV GX devices. This behavior can be seen both in simulation and in hardware. Offset cancellation is indicated by the busy signal being asserted high for 16 clock cycles in simulation or for a few thousand clock cycles in hardware.


2. This issue is observed only in simulation.  Busy signal is asserted high upon power-up with reconfig_reset asserted high. If reconfig_reset is asserted high upon power-up; offset cancellation will be held off until reconfig_reset is de-asserted. Hence, busy signal should actually be low until reconfig_reset de-asserted low.

The correct behavior for offset cancellation is as following:

1. If reconfig_reset is asserted after offset cancellation is done, offset cancellation should not run again, since it is a one time power-up event.

2. If reconfig_reset is asserted before offset cancellation is completed during power-up, then offset cancellation should be held off until reconfig_reset is de-asserted. Offset cancellation should run again when reconfig_reset is de-asserted first time after power-up.

3. If reconfig_reset is asserted upon power up; offset cancellation should be held off until reconfig_reset is de-asserted. busy signal should be low upon power up till reconfig_reset is de-asserted.

A patch is available to fix this problem for the Quartus II software versions 10.0 SP1 and 10.1. Download and install the appropriate patch from the links below:

Related Products

This article applies to 1 products

Cyclone® IV GX FPGA