Article ID: 000081248 Content Type: Troubleshooting Last Reviewed: 03/27/2023

Why is the efficiency of the Cyclone® V and Arria® V hard memory controller lower than expected for single port designs?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Multi-Port Front End (MPFE), used with the Hard Memory Controller for Arria® V and Cyclone® V devices, contains an arbiter that enables load balancing across multiple ports. In addition, the MPFE will always grant access to a different port after it has finished serving a port.

    This behavior means that where the MPFE only receives traffic on one port, either because no other ports have pending transactions or because a single port variation is generated, the controller will implement writes in 5 clock cycles instead of 4 clock cycles. Reads are not affected.

    This behavior may also be seen in multi-port MPFE configurations.

     

     

     

     

    Resolution

    There is no workaround for this behavior.

    Related Products

    This article applies to 11 products

    Arria® V GX FPGA
    Cyclone® V GT FPGA
    Arria® V GT FPGA
    Arria® V GZ FPGA
    Cyclone® V E FPGA
    Cyclone® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.