Article ID: 000074992 Content Type: Troubleshooting Last Reviewed: 04/01/2013

Why do I see hold time violations within the altera_reserved_tck clock domain to the node pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see hold time violations to this node in the Quartus® II software if you are using an IP product in OpenCore Plus evaluation mode. This hold time violation does note occur if you are using the IP with a valid license. This hold time violation does not affect device operation.

    Resolution

    You can safely ignore this hold time violation as this violation.

    If you would like to avoid this violation, set a false path to this node with the following constraint in your Synopsys Design Constraint (.sdc) file

    set_false_path -to [get_registers *|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967]

    This issue is fixed beginning with the Quartus II software version 12.1.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices