Article ID: 000078108 Content Type: Troubleshooting Last Reviewed: 04/22/2013

Can I directly instantiate a Verilog HDL entity in a VHDL design file by referencing the library?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a limitation in the Quartus® II synthesis, you cannot directly instantiate a Verilog HDL module in a VHDL design file by referencing it with the library. For example, you cannot instantiate a Verilog HDL module using the following syntax:

    <Verilog HDL instance>: entity <library name>.<Verilog HDL module>
    Resolution

    To work around this limitation, create a component declaration for the Verilog HDL module before instantiating it. The component can be declared in a package or in the architecture section of the design.

    This limitation is scheduled to be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices