Description
This error may occur in the Quartus® II software version 8.1, if your HDL code infers a true dual-port synchronous RAM, but one of the output data ports is unconnected in your design.
Resolution
To work around this error, connect the unconnected output data port to registers in your HDL code.
Note that if these registers have no fan out, you can use the noprune synthesis attribute or the Preserve Fan-out Free Register Node logic option, to prevent the registers from being removed during synthesis. Refer to the Quartus II Integrated Synthesis chapter of the Quartus II Handbook for details on this attribute or logic option.
This problem is fixed beginning with the Quartus II software version 10.0.