Article ID: 000080689 Content Type: Troubleshooting Last Reviewed: 02/13/2006

Why when I use DSP Builder version 1.0. does my design simulate correctly in software, but does not operate in hardware?

Environment

  • DSP Builder for Intel® FPGAs Pro Edition
  • DSP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description You can get this problem if your design contains delay blocks and you have not explicitly assigned the global reset to an input pin tied to a known value on the board. DSP Builder automatically creates a global synchronous reset for delay blocks. If, during place and route you assign the global reset to a pin that is left unconnected on your board, the output of the delay blocks will be in an unknown state.

    If you do not wish to use the global reset, you must assign it to a pin that is tied to ground on your board.

    If you are using the DSP Development Board, for example, you can assign the reset to any of the fast I/O pins, which are grounded. All pin assignments must be made in the Quartus® II software.

    If you wish to use the global reset, you must assign it to a pin that can be driven by a logic level 1 or a logic level 0 on your board. If you are using the DSP development board, you can assign the global reset to one of the four pins connected to side switches.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices