Article ID: 000080752 Content Type: Troubleshooting Last Reviewed: 12/11/2007

Can Quartus II synthesis infer a small asynchronous memory structure that can be placed in a Stratix III MLAB block?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

By default, the Quartus® II software version 6.1 and 7.0 does not infer memory structures targeted for Stratix® III MLAB blocks from HDL code. You must use a ramstyle attribute with the value MLAB so that the Quartus II software can infer a small RAM block and place it in an MLAB.

In addition, some asynchronous RAM blocks may be coded with read-during-write behavior that does not match the Stratix III architecture. Thus the device behavior would not exactly match the behavior described in the code. If the difference in behavior is acceptable in your design, use the ramstyle attribute with the no_rw_check value to specify that the software should not check the read-during-write behavior when inferring the RAM. When this attribute is set, Quartus II integrated synthesis allows the behavior of the output to be different when the asynchronous read occurs on an address that had a write on the most recent clock edge.  That is, functional HDL simulation results will not match the hardware behavior if you write to an address that is being read.

To include both attributes, set the value of the ramstyle attribute to "MLAB, no_rw_check". For information about the syntax for setting synthesis attributes, refer to the Quartus II Integrated Synthesis (PDF) chapter in volume 1 of the Quartus II Handbook.

The following is a Verilog-2001 example of a small asyncronous RAM block, with the ramstyle synthesis attribute set so that the memory can be implemented in the MLAB memory block and the read-during-write behavior is not important. Without the attribute, this design requires 512 registers and 240 ALUTs. With the attribute, the design requires 8 memory ALUTs and just 15 registers.

module async_ram (
    input   [5:0] addr,
    input   [7:0] data_in,
    input         clk,
    input         write,
    output  [7:0] data_out );
 
   (* ramstyle = "MLAB, no_rw_check" *) reg [7:0] mem[0:63];
 
   assign  data_out = mem[addr];
 
   always @ (posedge clk)
   begin
      if (write)
         mem[addr] = data_in;
   end
endmodule

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