Are there any known issues regarding the timing constraint file for CPRI IP core v10.0?

Yes.Please remove the following constraints on the Rx PCS-PCD paths in the SDC file generated by CPRI IP core:

set_multicycle_path -from [get_clocks {*receive_pcs0|recoveredclk rxclk_div4 rxclk_div2}] -to [get_clocks rxclk] -setup -end 2
set_multicycle_path -from [get_clocks {*receive_pcs0|recoveredclk rxclk_div4 rxclk_div2}] -to [get_clocks rxclk] -hold -end 2

And then add the following constraint in the SDC file generated by CPRI IP core:
If {$::quartus(nomeofexecutable) == “quartus_fit”} {
   set_min_delay –from {*wire_receive_pcs0_dataoutfull*} –to {*|buf_wr_data*} 1.500
}

In CPRI IP core v10.1 we have eliminated all the multi-cycle constraints in the SDC file and fix the RTL code with updated SDC file.