Critical Issue
The 10.3125-Gbps Interlaken MegaCore function variations with
transceivers require a different ref_clk
frequency
than they were originally designed for. If you use the Interlaken
12-lane, 10-Gbps variation as generated, the lane rate is 10.2 Gbps
rather than 10.3125 Gbps, in simulation and when programmed on the
device.
Therefore, in addition to running the ref_clk
input
clock at 322.265625 MHz as specified in the
Interlaken MegaCore Function User Guide, you must also make
some manual modifications to several of the RTL files.
After you generate your Interlaken variation and before you simulate your design, follow these steps to modify your RTL files to fix the underlying problem:
- Edit the file alt_ntrlkn_gxb_10g.v with
the correct values to match the 322.265625-MHz
ref_clk
frequency by following these steps: - Edit the submodules/<variation>.sdc file with the correct clock frequencies by following these steps:
To set the correct effective data rate, replace every instance
of 10200
with 10312.5
.
To set the correct input period, replace every instance of 3137
with 3103
.
To set the correct input clock frequency, replace every instance
of 318.75
with 322.265625
.
Set tx_mac_c_clk
frequency to 257.81 MHz.
Set the rx_mac_c_clk
frequency to 257.81 MHz.
If you are using the Qsys design example provided with the Interlaken IP installation, follow these additional steps:
- In the alt_interlaken_12lane_10g.sdc file in the project directory, set the following clock frequencies:
- In the testbench/alt_interlaken_12lane_10g_tb.sv file,
update the
ref_clk
frequency by replacing#1568
with#1551.5
.
Set the Sample Channel Client clock frequencies to 257.81 MHz
Set the tx_mac_c_clk
frequency to 257.81 MHz
Set the rx_mac_c_clk
frequency to 257.81 MHz
Set the ref_clk
frequency to 322.265625 MHz
This issue is fixed in version 11.0 of the Interlaken MegaCore function.