Critical Issue
Qsys does not support the following Avalon Memory-Mapped (Avalon-MM)
flow control signals: dataavailable, readyfordata, endofpacket,
and flush.For components that use the deprecated Memory-Mapped
flow control, Qsys issues warnings during generation. For the Altera
Avalon JTAG UART and DMA Controller components, Qsys generates messages
similar to the following:
Warning: “No matching role found for jtag_uart_0:avalon_jtag_slave:dataavailable
(dataavailable)”
Warning: “No matching role found for dma_0:read_master:read_flush (flush)”
You may safely ignore these messages for Altera components because the signals are not required for design operation.If generation of a Qsys system produces similar messages for a custom component or IP block, check with the custom component or IP block author to ensure that the signals listed are not required.